EnSilica provide a comprehensive range of encryption and authentication IP which balances silicon area with throughput..

The Cryptographic IP cores are available stand-alone or as AMBA APB memory mapped peripherals.  The algorithms supported include:

  • RSA
  • AES
  • SHA for WLAN, WIMAX and IPsec
  • SNOW3G for LTE
  • TDES for compatibility with legacy systems
  • TRNG
  • DES

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Configurable Embedded RISC Processor IP

eSi-RISC is a highly configurable microprocessor architecture for embedded systems, that scales across a wide range of applications.

The RISC IP core has been silicon proven in a number of ASIC and FPGA technologies.

  • Configurable 16 or 32-bit, 5-stage pipelined RISC, load-store architecture.
  • Implemented in as little as 8k ASIC gates for minimum 16-bit configuration.
  • Intermixed 16 and 32-bit instructions gives exceptional code density.
  • Uses industry standard bus architecture for IP interconnection (AMBA AXI/AHB/APB).
  • Configurability and custom instructions will deliver a solution with exceptionally low-power.
  • Choice of von Neumann or Harvard memory architecture.
  • Supports user and supervisor modes.
  • JTAG or serial hardware debug.
  • Applications include smart sensors, IoT, touch screen controllers, medical, power management, metering, wireless or mobile products.

eSi- RISC family includes eSi-1600, eSi-1650, eSi-3200, eSi-3250, eSi-3260

Know more about EnSilica’s eSi-RISC