16-bit RISC IP, Low-Cost & Low-Power CPU with Cache
EnSilica’s eSi-1650 16-bit RISC IP core is an extremely small, low-power processor with the option of instruction and/or data cache. The low-gate count and cache feature provides a very power and area efficient solution for mature process nodes using OTP or Flash for program memory.
16 bit RISC IP: eSi-1650 Technical Overview
- 16-bit RISC architecture
- Optional instruction and/or data cache
- 16 general purpose registers
- 92 basic instructions and 10 addressing modes
- Supports up to 90 user-defined instructions
- 5-stage pipeline
- Harvard or von Neumann memory architecture
- AMBA AHB and APB peripheral bus
- Optional support for user and supervisor modes
- Up to 16 interrupts plus NMI and system call
- Fast interrupt response time of 6-9 cycles
- JTAG or serial debug
- Up to 2.81 CoreMark per MHz
- High code density
- ASIC performance (Typical 0.13um):
- Up to 600 MHz
- From 8.5k gates
- From 15uW/MHz
- FPGA Performance (Virtex 5):
- Up to 160 MHz
- From 1100 LUTs
- High quality IP:
- Verilog RTL
- DFT ready
- Silicon proven
- C and C++ software development using license-free toolchain, under industry standard Eclipse IDE
- Easy migration path to 32-bit version
- Touch screen controllers
- Smart sensors for IoT
- Home automation
- Industrial control
- Low-power wireless
- Data communication
- Power management
The eSi-1650 16-bit CPU with optional instruction and/or data cache. I t is targeted specifically for low-cost and low-power applications, where typically an 8-bit CPU may have previously been used, or where a 32-bit CPU is too big or power hungry. The instruction cache provides and area and power efficient solution when running from on-chip NVM or Flash. The use of the cache allow higher CPU performance when running from mature technologies as the performance is normally limited by the memory speed.
Even though it is 16-bit, the gate count is equivalent to many 8-bit cores due to the simplicity of the RISC pipeline. With a wider datapath and 16 general purpose registers, application programs are able to execute in far fewer clock cycles. This can save a significant amount of power by either allowing the CPU to be clocked at a lower frequency or by being able to enter a power down state sooner.
For applications where high performance is required, the 5-stage pipeline allows extremely high clock frequencies to be achieved. The optimising C/C++ compiler is fully aware of the pipeline and is able to schedule instructions to eliminate latencies. Static branch prediction is employed to minimize the cost of branch instructions.
The instruction set includes arithmetic and logical instructions (including barrel-shift, multiply and divide), comparisons, load and stores, branches and calls as well as system level instructions to control interrupts and enter lower power states. There are also a number of optional instructions and addressing modes that can be selected, should a specific application require them. For those applications that require extreme performance or ultra low power, user-defined instructions and registers can be implemented.
Hardware debug facilities include hardware breakpoints, watchpoints, null pointer detection and single-stepping for fast debugging of ROM, FLASH and RAM based programs.
The toolchain is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customizable Eclipse IDE. The debugger can connect to the target CPU either via JTAG, a serial interface or the Verilog PLI.
Complete C and C++ libraries are supplied. Ports of Micrium’s uC/OS-II RTOS, FreeRTOS and the lwIP TCP/IP stack are available. The toolchain is available for both Windows and Linux hosts and is available to use at no cost.
eSi-RISC is delivered as a Verilog RTL IP core. The design is target technology independent, although alternative implementations of some modules are available, such as the multiplier and JTAG interface, which are specifically optimised for FPGAs. The design is DFT ready, supporting full scan insertion for all flip flops and memory BIST. Example scripts are provided for popular EDA tools.
A selection of AMBA peripherals are supplied with the core, including: UART, SPI, I2C™, Timer, PWM, Watchdog, GPIO, PS/2 and Ethernet MAC. By using an industry standard bus, a wide range of 3rd party IP cores are also compatible with eSi-RISC.