Configurable Embedded RISC Processor IP
eSi-RISC is a highly configurable microprocessor architecture for embedded systems, that scales across a wide range of applications.
The RISC IP core has been silicon proven in a number of ASIC and FPGA technologies.
- Configurable 16 or 32-bit, 5-stage pipelined RISC, load-store architecture.
- Implemented in as little as 8k ASIC gates for minimum 16-bit configuration.
- Intermixed 16 and 32-bit instructions gives exceptional code density.
- Uses industry standard bus architecture for IP interconnection (AMBA AXI/AHB/APB).
- Configurability and custom instructions will deliver a solution with exceptionally low-power.
- Choice of von Neumann or Harvard memory architecture.
- Supports user and supervisor modes.
- JTAG or serial hardware debug.
- Applications include smart sensors, IoT, touch screen controllers, medical, power management, metering, wireless or mobile products.