Logical Implementation

Logical Implementation covers the RTL-to-Netlist stages of an ASIC development flow. This used to involve mainly synthesis to meet timing and area targets, plus some scan-insertion for DFT, but now covers a wider range of activities that can be critical to the optimisation and performance of your ASIC, including:

  • RTL and DFT optimisation for performance, power, and area
  • Synthesis trials to help select the ideal silicon process and IP for your application
  • Insertion of Test and BIST structures into the RTL
  • Synthesis of power management and power optimisation logic, using UPF/CPF
  • Technology-specific IP integration, such as SRAM, eFlash, and other 3rd-party IP
  • Timing constraint generation for STA

EnSilica can help make sure that your RTL is suitable and optimised for ASIC implementation, and can take on all of the tasks needed to produce a netlist that is ready for physical implementation.

Logical Implementation Services

  • Synthesis

    Synthesis is the conversion from RTL to netlist for a specific ASIC technology. It is an automated process but needs well-written RTL, correct timing constraints, and sometimes expert knowledge of the EDA tool behaviour to yield optimum results.  Whatever your specific design goals, EnSilica can work with your requirements and the latest EDA tool flows to ensure that the synthesis process produces the best possible results.

  • Design for Test (DFT)

    DFT is now becoming a specialised implementation area, but one that is often not considered early enough during architectural or RTL-level design.

    EnSilica have expertise in developing and integrating a complete test strategy for your ASIC design to deliver high fault coverage. DFT techniques that can be applied to your design include:

    • Scan insertion, including test compression synthesis
    • Testing of embedded IP (e.g hard IP/Analog/PHY)
    • SRAM BIST and repair
    • JTAG TAP and boundary-scan insertion
    • ATPG, including power-aware and advanced defect detection

    Also, as part of a turn-key ASIC development, EnSilica can take on the selection and management of production test facilities, and will oversee the development of all the hardware and software needed to bring up a production-ready test solution.

  • Power Optimisation

    Some of the power-management techniques that can be applied to a design are implemented during RTL synthesis. These include:

    • Clock-gating insertion
    • Supporting logic for power-management, e.g. level-shifters and isolator cells
    • Logic gating to reduce dynamic power

    EnSilica have the skills needed to implement these techniques and can also develop UPF (or CPF) scripts to specify the power-management intent for all the EDA tools involved in the generation and verification of the netlist.

  • Static Timing Analysis (STA)

    Developing a complete and correct set of timing constraints is a fundamental requirement for robust ASIC implementation.

    Increased levels of integration, complex internal clocking modes, and the increasing use of standards-based IO and interfaces mean that timing constraint generation is now a relatively specialised task, and is often one that our customers are not fully confident in taking on by themselves.

    EnSilica have extensive experience developing both interface and internal ASIC timing constraints for synthesis, place-and-route, and final timing sign-off. Our engineers also work closely with the physical implementation team to ensure that timing margins and methodology are always appropriate for the target silicon process.

  • Logical Equivalence

    EnSilica undertake logical equivalence checking (LEC) across all stages in the implementation flow to confirm that all the processing steps that are applied to the design, such as synthesis, DFT-insertion, and place-and-route, have not affected the functionality specified by the RTL.