ASIC Services

High quality HDL code ensures good quality of results from synthesis and facilitates efficient reuse. EnSilica has extensive experience in creating a broad range of designs using both Verilog and VHDL, based upon a robust set of coding guidelines.  We have extensive expertise in low-power design techniques and are skilled in IP integration and design for reuse methodology. Our highly productive design team has proven ability in taking designs from specification through to fully verified RTL.

The ability to develop a high quality verification strategy is one of the key activities that will determine the success of your ASIC project. Get it wrong and you are looking at a silicon re-spin with typically a 6 – 12months delay in getting your product to market with substantial cost and revenue implications.

EnSilica can help identify the right verification strategy for your design, one that will provide high confidence that the functional requirements defined in the specification are indeed implemented correctly. Learn more about our Advanced ASIC Verification services.

EnSilica are members of the Mentor Graphics Questa Vanguard Program (QVP) and Cadence Verification Alliance Program.

EnSilica have the expertise needed to support the logical implementation of your design, including synthesis, DFT/ATPG/MBIST,  STA, and Logical Equivalence. We can then interface with your chosen layout  team, whether this be EnSilica, your own team, or a 3rd party layout company, to help make sure you get optimum results at the physical implementation stage.  Learn more about our ASIC Implementation services.

EnSilica can support the physical design of your chip from netlist all the way through to generation of GDSII ready for foundry tapeout.  Physical design includes floorplanning, clock-tree synthesis, place-and-route, timing closure, power optimisation, and sign-off verification.  Benefiting from detailed knowledge gained through the logical implementation and verification activities, EnSilica are perfectly placed to undertake the physical design and ensure that your design reaches tapeout as quickly as possible.

EnSilica are able to deploy the full range of tools from the leading EDA vendors (Synopsys, Cadence, and Mentor) for ASIC implementation and verification. Our engineers have a broad range of experience with different tool-chains, and will often optimise tool choice according to the complexity of the design and the chosen ASIC technology.

EnSilica’s engineering team have experience of working with a wide range of semiconductor technologies from all the  major ASIC vendors and foundries.  Recent projects have covered a range of processes from 0.18u down to 28nm, including Mixed Signal (MS), High Voltage(HV), and embedded Flash (eFlash) variants.  EnSilica can conduct feasibility or technology trials to help determine the optimum semiconductor process for a particular project, and to explore the trade-offs that can be made across different process options.

Energy conservation is now often a key performance goal for designers when considering ASIC implementation.  EnSilica have the experience and skills needed to apply a full range of power-saving and power-management techniques to your ASIC design, and to implement and verify these throughout the ASIC development flow. Learn more about our Logical Implementation and Physical Design services.